An AI and server computing architecture designed to compute data where it is stored, reducing the energy and delay of repeatedly moving data between memory and processors. It combines nonvolatile memory, mixed analog and digital computation, adaptable interconnects and integrated thermal control.

The architecture supports retained learning and immediate recovery of stored model state after power loss. Applications extend from AI accelerators and server CPUs to robotics, neuromorphic systems and sensor-side computing.

For the pitch’s 70-billion-parameter model with 1,024 concurrent users, digital-mode estimates target 8–35 times less energy per token and 8–35 times more tokens per second per watt than the H100 comparison. Estimated cost per million tokens is about 8–32 times lower under the stated model assumptions. Gains vary with workload and concurrency.

The data-center scenario estimates 65–97% less chip power for equivalent work. Robotics applications target onboard conversational AI, direct sensor processing and continual learning. The proposed manufacturing route uses existing semiconductor equipment without requiring 4 nm or finer scaling.

These are modeled development targets, subject to device, prototype and application validation.

Detailed computing architecture, engineering structures, device implementation, manufacturing parameters and software tools can be discussed after signing a non-disclosure agreement (NDA).